性别要求：不限性别
Job Responsibilities1. Be responsible for advanced chip implementation flow development, chip PPA boost, an d support headquarter advanced technology for EDA router engagement2. ASIC block-level implementation and/or full-chip integration projects3. Develop IC design methodology
Requirement of capability1.MS Ｏr BS in CS, EE related field with experience in APR, physical verification, chip implementation, Ｏr CAD algorithm.2. Expert in ASIC RTL-to-GDS design flow3.Solid skill sets of Cadence/Synopsys/Mentor EDA tools4.Experience with TSMC 40nm technology5. Experience in implementation signoff6.Proven record in production tapeouts7.Experience in tapeout with multi-million gates Ｃount SOC design. 28nm/40nm design experience is a plus.8.Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM an d spice simulations.9.Experience in CAD methodology an d problem solving skill10.Familiar with Verilog, Perl/Tcl an d C/C 11.Good communication in English
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